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yourfanat wrote: I am using another tool for Oracle developers - dbForge Studio for Oracle. This IDE has lots of usefull features, among them: oracle designer, code competion and formatter, query builder, debugger, profiler, erxport/import, reports and many others. The latest version supports Oracle 12C. More information here.

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GLOBALFOUNDRIES and Samsung Support New Cadence Virtuoso Advanced Node for 20- and 14nm Processes

SAN JOSE, CA -- (Marketwire) -- 02/05/13 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that two of its major foundry partners -- Samsung Foundry and GLOBALFOUNDRIES -- are supporting new Cadence® custom/analog technology targeting designs at the advanced nodes of 20 and 14 nanometers. The two foundries are providing SKILL-based process design kits (PDKs) for the newly introduced Cadence Virtuoso® Advanced Node.

"Moving to 20 and 14 nanometers presents numerous new manufacturing challenges, so we have been working closely with Cadence to help our mutual customers over the hurdles," said Andy Brotman, vice president, Design Infrastructure at GLOBALFOUNDRIES. "Providing PDKs that meet customer demand for features like native SKILL PCells and real-time dynamic coloring is an essential element for the ecosystem to develop the foundation IP necessary to bring these new technologies to designers."

"Manufacturing designs at Samsung's 14-nanometer process requires advanced technology and methodologies that can tackle new requirements like double patterning and FinFETs," said Dr. Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions at Samsung Electronics. "With the Samsung-developed new SKILL-based PDK for our 14-nanometer process node, our customers can now improve design start-up time, boost designer productivity, and improve design quality."

Virtuoso Advanced Node addresses the toughest challenges facing engineers, including layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. The new technology integrates seamlessly with the Cadence Integrated Physical Verification System (IPVS) -- technology for DRC and DPT checking -- to conduct on-the-fly checks that reduce layout iterations.

"Virtuoso Advanced Node provides many new functionalities to enable our customers' designs at the most advanced nodes of 20 and 14 nanometers," said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. "And with their SKILL-based PDKs for these new process nodes, our foundry partners continue to provide the enablement necessary to ensure these complex designs will be successfully and profitably manufactured."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, Virtuoso and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com

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