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Advantest's New Test Cell Selected by Marvell Semiconductor to Reduce Cost of Test for High-Volume, Cost-Sensitive ICs
Based on Evaluation Unit's High Performance, the x16 Parallel Test Cell Has Been Released for Production for Marvell Products
By: Marketwired .
Jan. 8, 2013 03:05 AM
TOKYO, JAPAN -- (Marketwire) -- 01/08/13 -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) (NYSE: ATE) today announced that the company has installed the first evaluation unit of its new test cell at Marvell (NASDAQ: MRVL), integrating the company's T2000 Enhanced Performance Package (EPP) and its M4841 Dynamic Test Handler. The T2000+M4841 Test Cell, capable of handling up to 16 devices in parallel, is designed to achieve the industry's lowest cost on final testing of high-volume, cost-sensitive semiconductors, including baseband processors, application processors, microprocessors, microcontrollers and highly integrated power-management integrated circuits (PMICs).
"Marvell and Advantest are pioneering market leaders in this test cell technology," said Albert Wu, vice president of manufacturing operations for Marvell Semiconductor, Inc. "Working together, we are developing a highly flexible, cost-effective solution for chip characterization and production on the same platform."
"While we continue to expand our test cell capabilities, Advantest is also preparing to meet growing customer demand as IC production volumes grow throughout global markets," said Mak Nakahara, senior vice president of Advantest Corporation.
The evaluation unit has been in trial use at Marvell's engineering center since January 2012. Based on measured performance, the x16 Test Cell has been released for production for Marvell products.
The T2000+M4841 Test Cell leverages the T2000 EPP's industry-leading parallel efficiency, innovative computing, bus architecture and high-density instrumentation to test as many as 16 complex system-on-chip (SoC) devices at one time without sacrificing accuracy or overall throughput. With the industry's largest socket area on its load boards, the T2000's test head architecture maximizes the number of devices that can be tested simultaneously, while also simplifying the linkage with Advantest's M4841 test handler. The handler is optimized for high throughput and low testing cost. It also maintains a high mean contact between jams (MCBJ) and the handler's soft-touch feature safeguards singulated IC packages from scratches and other potential damage. As a result, the integrated T2000+M4841 Test Cell offers customers the highest parallel final-test capabilities for the broadest range of SoC devices.
Advantest's T2000 EPP uses multiple tester controllers, instrumentation architecture and its unique large load board area to address the specific needs of today's complex microprocessors as well as consumer and wireless devices. Its scalability and multi-function, high-channel-density instrumentation enables this tester to meet SoC test requirements while delivering the industry's most economical cost-of-test advantages.
Unique in its class, Advantest's M4841 Dynamic Test Handler facilitates high-throughput parallel testing of complex ICs and packages such as ball grid arrays (BGAs), chip-scale packages (CSPs) and quad flat packages (QFPs). Because of its advanced performance capabilities and features, including its field-upgradable Tri-Temp capability, the M4841 system is optimal for high-volume production of devices used in consumer applications such as portable digital equipment and automotive electronics. With its high level of efficiency, this handler contributes substantially to reducing the cost of test.
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