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REMINDER: At EDSFair, Blue Pearl Demos FPGA Design Tools for RTL Signoff, Presents on Overcoming Timing Challenges
By: Marketwired .
Nov. 11, 2012 05:00 PM
YOKOHAMA, JAPAN -- (Marketwire) -- 11/11/12 --
For information, on Blue Pearl's longest path analysis, please click here to read our article Find and Analyze the Longest Combinational Paths, Meet Performance Goals.
For information on how Blue Pearl enables SoC RTL analysis, click here to read our white paper, RTL analysis for complex FPGA designs using a Grey Cell methodology.
About the Blue Pearl Software Suite for FPGA RTL Signoff
The company's collaboration with Synopsys offers an optimized flow that works with Synopsys' Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with Synopsys' synthesis flow.
About Blue Pearl Software
Visit Blue Pearl Software at http://www.bluepearlsoftware.com.
Visual Verification Environment is a trademark of Blue Pearl Software, Inc.
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